The present invention relates to a method for performing direct wafer-to-wafer bonding, including wafer multi-stacking, through metal features such as metal pads, lines, or patterns, on surfaces of the wafer to one another, prior to severing the joined wafers into individual units each containing a chip of a wafer and a chip of another wafer bonded to the wafer.
Assemblies of vertically stacked semiconductor chips having direct vertical electrical interconnections using through silicon vias (TSV) offer improvements in integration density and speed of information access.
Wafer-to-wafer bonding techniques can be used to join wafers together in vertically stacked wafer assemblies, which can then be diced into individual stacked semiconductor chip assemblies containing stacks of two or more semiconductor chips each. Each individual stacked semiconductor chip assembly may have through silicon vias extending in a vertical direction of the assembly for electrically connecting the chips therein. Wafer-to-wafer bonding techniques include metal-to-metal bonding in which flat metal elements, typically a plurality of discrete metal pads, at a surface of one wafer are joined with corresponding flat metal elements at a surface of a second wafer.
Metal-to-metal bonding techniques are subject to variations in bond strength between wafers due to misalignment between the metal elements of one wafer relative to the metal elements of another wafer to which they are to be bonded. Such misalignment can result in metal to oxide contact in a non-controlled fashion, or metal elements of one wafer not bonding with those of the other wafer.
Hybrid bonding, in which metal elements of respective wafers bond together as well as oxide elements of the respective wafers, leave large portions of the respective wafers unbonded, which include among others, kerf regions disposed between adjacent undiced semiconductor chips of a wafer. The unbonded areas can provide a potential source of cracking or chipping defects when dicing a stacked wafer assembly into a plurality of individual stacked semiconductor chip assemblies, especially in the case of wafer multi-stacking.
Despite these existing ways of joining wafers to one another, further improvements can be made.